Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.
How to
Safety WDTInitial How to Disable
Change
M103C
WDTON
Level
State
the WDT
Time-out
Unprogrammed Unprogrammed
1
Disabled
Timed
Timed
sequence
sequence
Unprogrammed Programmed
2
0
2
Enabled
Disabled
Enabled
Always enabled
Timed
sequence
Programmed
Programmed
Unprogrammed
Programmed
Timed
sequence
No
restriction
Always enabled
Timed
sequence
Figure 28. Watchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer
Control Register –
WDTCR
Bit
7
–
6
–
5
–
4
WDCE
R/W
0
3
WDE
R/W
0
2
1
WDP1
R/W
0
0
WDP2
R/W
0
WDP0
R/W
0
WDTCR
Read/Write
Initial Value
R
0
R
0
R
0
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits. See “Timed Sequences for Changing the
Configuration of the Watchdog Timer” on page 58.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
56
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
