PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
f
clk_I/O
f
= -----------------
OCnPCPWM
N ⋅ 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in Figure 67 OCn has a transition from high to low even though there
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without a Compare Match:
•
OCR2A changes its value from MAX, like in Figure 67. When the OCR2A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
•
The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
154
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
