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ATMEGA128L-8AL 参数 Datasheet PDF下载

ATMEGA128L-8AL图片预览
型号: ATMEGA128L-8AL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 391 页 / 6192 K
品牌: ATMEL [ ATMEL ]
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ATmega128(L)  
Output Compare  
Register 3 B –  
Bit  
7
6
5
4
3
2
1
0
OCR3BH and OCR3BL  
OCR3B[15:8]  
OCR3B[7:0]  
OCR3BH  
OCR3BL  
R/W  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
R/W  
0
R/W  
0
R/W  
0
0
0
Output Compare  
Register 3 C –  
Bit  
7
6
5
4
3
2
1
0
OCR3CH and OCR3CL  
OCR3C[15:8]  
OCR3C[7:0]  
OCR3CH  
OCR3CL  
R/W  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
R/W  
0
R/W  
0
R/W  
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the  
counter value (TCNTn). A match can be used to generate an output compare interrupt, or to  
generate a waveform output on the OCnx pin.  
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are  
written simultaneously when the CPU writes to these registers, the access is performed using an  
8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other  
16-bit registers. See “Accessing 16-bit Registers” on page 115.  
Input Capture Register  
1 – ICR1H and ICR1L  
Bit  
7
6
5
4
3
2
1
0
ICR1[15:8]  
ICR1[7:0]  
ICR1H  
ICR1L  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
0
Input Capture Register  
3 – ICR3H and ICR3L  
Bit  
7
6
5
4
3
2
1
0
ICR3[15:8]  
ICR3[7:0]  
ICR3H  
ICR3L  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the  
ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-  
ture can be used for defining the counter TOP value.  
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read  
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit  
temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit  
registers. See “Accessing 16-bit Registers” on page 115.  
Timer/Counter  
Interrupt Mask  
Register – TIMSK  
Bit  
7
OCIE2  
R/W  
0
6
TOIE2  
R/W  
0
5
TICIE1  
R/W  
0
4
OCIE1A  
R/W  
0
3
OCIE1B  
R/W  
0
2
TOIE1  
R/W  
0
1
OCIE0  
R/W  
0
0
TOIE0  
R/W  
0
TIMSK  
Read/Write  
Initial Value  
Note:  
This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are  
described in this section. The remaining bits are described in their respective timer sections.  
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable  
139  
2467P–AVR–08/07  
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