11. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
11.1 Sleep Modes
Figure 10-1 on page 39 presents the different clock systems in the
ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an
appropriate sleep mode. Table 11-1 shows the different sleep modes and their wake-up
sources.
Table 11-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains Oscillators Wake-up Sources
Sleep Mode
Idle
X
X
X
X
X
X
X
X(2)
X(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADCNRM
X(3)
X(3)
X(3)
X(3)
X(3)
X(2)
Power-down
Power-save
Standby(1)
X
X(2)
X
X
X
X
Extended Standby
X(2)
X(2)
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
To enter any of the sleep modes, the SE bit in “SMCR – Sleep Mode Control Register” on page
56 must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and
SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruc-
tion. See Table 11-2 on page 56 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
11.2 Idle Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Inter-
face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
52
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
