ATmega640/1280/1281/2560/2561
Figure 9-5. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
T6
T7
System Clock (CLKCPU
)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
Address
Data
Address
Address
XX
DA7:0 (XMBK = 0) Prev. data
DA7:0 (XMBK = 1) Prev. data
RD
Data
Data
Address
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
9.1.5
Using all Locations of External Memory Smaller than 64 KB
Since the external memory is mapped after the internal memory as shown in Figure 9-1, the
external memory is not addressed when addressing the first 8,704 bytes of data space. It may
appear that the first 8,704 bytes of the external memory are inaccessible (external memory
addresses 0x0000 to 0x21FF). However, when connecting an external memory smaller than 64
KB, for example 32 KB, these locations are easily accessed simply by addressing from address
0x8000 to 0xA1FF. Since the External Memory Address bit A15 is not connected to the external
memory, addresses 0x8000 to 0xA1FF will appear as addresses 0x0000 to 0x21FF for the
external memory. Addressing above address 0xA1FF is not recommended, since this will
address an external memory location that is already accessed by another (lower) address. To
the Application software, the external 32 KB memory will appear as one linear 32 KB address
space from 0x2200 to 0xA1FF. This is illustrated in Figure 9-6.
31
2549L–AVR–08/07
ATMEL [ ATMEL ]
