ATmega640/1280/1281/2560/2561
Table 22-1. Equations for Calculating Baud Rate Register Setting
Equation for Calculating Equation for Calculating
Operating Mode
Baud Rate(1)
UBRR Value
f
OSC
UBRRn = ----------------------- – 1
16BAUD
f
Asynchronous Normal
mode (U2Xn = 0)
OSC
BAUD = -----------------------------------------
16(UBRRn + 1)
f
OSC
UBRRn = -------------------- – 1
8BAUD
Asynchronous Double
Speed mode (U2Xn =
1)
f
OSC
BAUD = --------------------------------------
8(UBRRn + 1)
f
OSC
UBRRn = -------------------- – 1
2BAUD
f
OSC
Synchronous Master
mode
BAUD = --------------------------------------
2(UBRRn + 1)
UBRRn
Contents of the UBRRHn and UBRRLn Registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 22-9 on
page 228.
22.2.2
Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
22.2.3
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 22-2 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
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2549L–AVR–08/07
ATMEL [ ATMEL ]
