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ATMEGA2560-16AU-SL383 参数 Datasheet PDF下载

ATMEGA2560-16AU-SL383图片预览
型号: ATMEGA2560-16AU-SL383
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MS-026AED, TQFP-100]
分类和应用: 时钟微控制器
文件页数/大小: 448 页 / 7518 K
品牌: ATMEL [ ATMEL ]
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Table 16-4. Compare Output Mode, Phase Correct PWM Mode(1)  
COM0A1  
COM0A0  
Description  
0
0
Normal port operation, OC0A disconnected.  
WGM02 = 0: Normal Port Operation, OC0A Disconnected.  
WGM02 = 1: Toggle OC0A on Compare Match.  
0
1
1
1
0
1
Clear OC0A on Compare Match when up-counting. Set OC0A on  
Compare Match when down-counting.  
Set OC0A on Compare Match when up-counting. Clear OC0A on  
Compare Match when down-counting.  
Note:  
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on  
page 126 for more details.  
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode  
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0  
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected  
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin  
must be set in order to enable the output driver.  
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the  
WGM02:0 bit setting. Table 16-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits  
are set to a normal or CTC mode (non-PWM).  
Table 16-5. Compare Output Mode, non-PWM Mode  
COM0B1  
COM0B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.  
Toggle OC0B on Compare Match  
Clear OC0B on Compare Match  
Set OC0B on Compare Match  
Table 16-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM  
mode.  
Table 16-6. Compare Output Mode, Fast PWM Mode(1)  
COM0B1  
COM0B0  
Description  
Normal port operation, OC0B disconnected.  
Reserved  
0
0
0
1
Clear OC0B on Compare Match, set OC0B at BOTTOM,  
(non-inverting mode).  
1
1
0
1
Set OC0B on Compare Match, clear OC0B at BOTTOM,  
(inverting mode).  
Note:  
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on  
page 124 for more details.  
130  
ATmega640/1280/1281/2560/2561  
2549L–AVR–08/07  
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