ATmega640/1280/1281/2560/2561
Table 16-9. Clock Select Bit Description
CS02
CS01
CS00
Description
No clock source (Timer/Counter stopped)
clkI/O/(No prescaling)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
clkI/O/8 (From prescaler)
clkI/O/64 (From prescaler)
clkI/O/256 (From prescaler)
clkI/O/1024 (From prescaler)
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
16.9.3
TCNT0 – Timer/Counter Register
Bit
7
6
5
4
3
2
1
0
0x26 (0x46)
Read/Write
Initial Value
TCNT0[7:0]
TCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
16.9.4
OCR0A – Output Compare Register A
Bit
7
6
5
4
3
2
1
0
0x27 (0x47)
Read/Write
Initial Value
OCR0A[7:0]
OCR0A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
16.9.5
OCR0B – Output Compare Register B
Bit
7
6
5
4
3
2
1
0
0x28 (0x48)
Read/Write
Initial Value
OCR0B[7:0]
OCR0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
133
2549L–AVR–08/07
ATMEL [ ATMEL ]
