ATmega640/1280/1281/2560/2561
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
15.2.9
PCMSK0 – Pin Change Mask Register 0
Bit
(0x6B)
7
6
5
4
3
2
1
0
PCINT7
PCINT6
PCINT5
R/W
0
PCINT4
R/W
0
PCINT3
R/W
0
PCINT2
R/W
0
PCINT1
R/W
0
PCINT0
R/W
0
PCMSK0
Read/Write
R/W
R/W
Initial Value
0
0
• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
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2549L–AVR–08/07