AT90PWM2/3/2B/3B
Figure 25-1. Parallel Programming
+ 5V
PD1
RDY/BSY
OE
VCC
PD2
+ 5V
WR
PD3
AVCC
BS1
PD4
PD5
XA0
PB[7:0]
DATA
PD6
XA1
PAGEL
+ 12 V
PD7
RESET
PE2
BS2
XTAL1
GND
Table 25-7. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O Function
0: Device is busy programming, 1: Device is
ready for new command
RDY/BSY
PD1
O
OE
PD2
PD3
I
I
Output Enable (Active low)
Write Pulse (Active low)
WR
Byte Select 1 (“0” selects Low byte, “1” selects
High byte)
BS1
PD4
I
XA0
XA1
PD5
PD6
I
I
XTAL Action Bit 0
XTAL Action Bit 1
Program memory and EEPROM Data Page
Load
PAGEL
BS2
PD7
PE2
I
I
Byte Select 2 (“0” selects Low byte, “1” selects
2’nd High byte)
Bi-directional Data bus (Output when OE is
low)
DATA
PB[7:0]
I/O
Table 25-8. Pin Values Used to Enter Programming Mode
Pin
PAGEL
XA1
Symbol
Value
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
0
0
0
0
XA0
BS1
283
4317J–AVR–08/10
ATMEL [ ATMEL ]
