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AT40K05LV-3DQI 参数 Datasheet PDF下载

AT40K05LV-3DQI图片预览
型号: AT40K05LV-3DQI
PDF下载: 下载PDF文件 查看货源
内容描述: 5K - 50K盖茨FPGA协处理器与FreeRAM [5K - 50K Gates Coprocessor FPGA with FreeRAM]
分类和应用: 现场可编程门阵列可编程逻辑异步传输模式ATM
文件页数/大小: 67 页 / 1491 K
品牌: ATMEL [ ATMEL ]
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The Busing Network  
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus  
resources: a local-bus resource (the middle bus) and two express-bus (both sides)  
resources. Bus resources are connected via repeaters. Each repeater has connections  
to two adjacent local-bus segments and two express-bus segments. Each local-bus  
segment spans four cells and connects to consecutive repeaters. Each express-bus  
segment spans eight cells and leapfrogsor bypasses a repeater. Repeaters regener-  
ate signals and can connect any bus to any other bus (all pathways are legal) on the  
same plane. Although not shown, a local bus can bypass a repeater via a programma-  
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are  
implemented through pass gates in the cell-bus interface. Express/Express turns are  
implemented through separate pass gates distributed throughout the array.  
Some of the bus resources on the AT40K/AT40KLV are used as a dual-function  
resources. Table 2 shows which buses are used in a dual-function mode and which bus  
plane is used. The AT40K/AT40KLV software tools are designed to accommodate dual-  
function buses in an efficient manner.  
Table 2. Dual-function Buses  
Function  
Type  
Plane(s) Direction  
Comments  
Cell Output Enable  
Local  
5
Horizontal  
and Vertical  
RAM Output Enable Express  
2
Vertical  
Vertical  
Vertical  
Bus full length at array edge  
Bus in first column to left of  
RAM block  
RAM Write Enable  
RAM Address  
Express  
Express  
1
Bus full length at array edge  
Bus in first column to left of  
RAM block  
1 - 5  
Buses full length at array edge  
Buses in second column to left  
of RAM block  
RAM Data In  
Local  
Local  
1
2
Horizontal  
Horizontal  
Data In connects to local  
bus plane 1  
RAM Data Out  
Data out connects to local  
bus plane 2  
Clocking  
Express  
Express  
4
5
Vertical  
Vertical  
Bus half length at array edge  
Bus half length at array edge  
Set/Reset  
6
AT40K/AT40KLV Series FPGA  
0896CFPGA04/02