Table 1. AT40K/AT40KLV Family(1)
AT40K05
AT40K10
AT40K20
AT40K40
Device
AT40K05LV
5K - 10K
16 x 16
256
AT40K10LV
AT40K20LV
AT40K40LV
Usable Gates
Rows x Columns
Cells
10K - 20K
24 x 24
576
20K - 30K
32 x 32
1,024
40K - 50K
48 x 48
2,304
Registers
256(1)
576(1)
4,608
192
1,024(1)
2,304(1)
18,432
384
RAM Bits
2,048
8,192
I/O (Maximum)
128
256
Note:
1. Packages with FCK will have 8 less registers.
Description
The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with dis-
tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM,
8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data),
automatic component generators, and range in size from 5,000 to 50,000 usable gates.
I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin
PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for
AT40KLV.
The AT40K/AT40KLV is designed to quickly implement high-performance, large gate
count designs through the use of synthesis and schematic-based tools used on a PC or
Sun platform. Atmel’s design tools provide seamless integration with industry standard
tools such as Synplicity, ModelSim, Exemplar and Viewlogic.
The AT40K/AT40KLV can be used as a coprocessor for high-speed (DSP/processor-
based) designs by implementing a variety of computation intensive, arithmetic functions.
These include adaptive finite impulse response (FIR) filters, fast Fourier transforms
(FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required
for video compression and decompression, encryption, convolution and other multime-
dia applications.
Fast, Flexible and
Efficient SRAM
The AT40K/AT40KLV FPGA offers a patented distributed 10 ns SRAM capability where
the RAM can be used without losing logic resources. Multiple independent, synchronous
or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can
be created using Atmel’s macro generator tool.
Fast, Efficient Array and The AT40K/AT40KLV’s patented 8-sided core cell with direct horizontal, vertical and
diagonal cell-to-cell connections implements ultra fast array multipliers without using
Vector Multipliers
any busing resources. The AT40K/AT40KLV’s Cache Logic capability enables a large
number of design coefficients and variables to be implemented in a very small amount
of silicon, enabling vast improvement in system speed at much lower cost than conven-
tional FPGAs.
2
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
ATMEL [ ATMEL ]
