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AT40K05LV-3DQI 参数 Datasheet PDF下载

AT40K05LV-3DQI图片预览
型号: AT40K05LV-3DQI
PDF下载: 下载PDF文件 查看货源
内容描述: 5K - 50K盖茨FPGA协处理器与FreeRAM [5K - 50K Gates Coprocessor FPGA with FreeRAM]
分类和应用: 现场可编程门阵列可编程逻辑异步传输模式ATM
文件页数/大小: 67 页 / 1491 K
品牌: ATMEL [ ATMEL ]
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AT40K/AT40KLV Series FPGA  
Cache Logic Design  
The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing  
Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly)  
for building adaptive logic and systems. As new logic functions are required, they can be  
loaded into the logic cache without losing the data already there or disrupting the opera-  
tion of the rest of the chip; replacing or complementing the active logic. The  
AT40K/AT40KLV can act as a reconfigurable coprocessor.  
Automatic Component  
Generators  
The AT40K/AT40KLV FPGA family is capable of implementing user-defined, automati-  
cally generated, macros in multiple designs; speed and functionality are unaffected by  
the macro orientation or density of the target device. This enables the fastest, most pre-  
dictable and efficient FPGA design approach and minimizes design risk by reusing  
already proven functions. The Automatic Component Generators work seamlessly with  
industry standard schematic and synthesis tools to create the fastest, most efficient  
designs available.  
The patented AT40K/AT40KLV series architecture employs a symmetrical grid of small  
yet powerful cells connected to a flexible busing network. Independently controlled  
clocks and resets govern every column of cells. The array is surrounded by programma-  
ble I/O.  
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to  
2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for  
easy design migration in the same package footprint. The AT40K/AT40KLV series  
FPGAs utilize a reliable 0.6µ single-poly, CMOS process and are 100% factory-tested.  
Atmel’s PC- and workstation-based integrated development system (IDS) is used to cre-  
ate AT40K/AT40KLV series designs. Multiple design entry methods are supported.  
The Atmel architecture was developed to provide the highest levels of performance,  
functional density and design flexibility in an FPGA. The cells in the Atmel array are  
small, efficient and can implement any pair of Boolean functions of (the same) three  
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays  
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,  
high-speed busing network provides fast, efficient communication over medium and  
long distances.  
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