AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Async RAM
Write
Parameter
Path
-2
Units
Notes
tWECYC (Minimum)
cycle time
8.0
3.0
3.0
2.0
0.0
2.0
0.0
4.6
3.1
1.6
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tWEL (Minimum)
we
Pulse width low
Pulse width high
Write
t
WEH (Minimum)
AWS (Minimum)
we
Write
t
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
Write
tAWH (Minimum)
Write
t
DS (Minimum)
DH (Minimum)
Write
t
Write/Read
Read
tDD (Maximum)
rd addr = wr addr
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
Read
Read
oe -> dout
Sync RAM
Write
t
CYC (Minimum)
cycle time
8.0
3.0
3.0
2.0
0.0
2.0
0.0
2.0
0.0
3.5
3.1
1.6
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tCLKL (Minimum)
clk
Pulse width low
Pulse width high
Write
tCLKH (Minimum)
tWCS (Minimum)
tWCH (Minimum)
tACS (Minimum)
tACH (Minimum)
tDCS (Minimum)
clk
Write
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
Write
Write
Write
tDCH (Minimum)
Write/Read
Read
tCD (Maximum)
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
rd addr = wr addr
rd addr -> dout
oe -> dout
Read
Read
oe -> dout
28
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
ATMEL [ ATMEL ]
