AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
.
.
Cell Function
Global Clocks and Set/Reset
PD (Maximum)
Parameter
Path
Device
-2
Units
Notes
GCLK Input Buffer
FCLK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
t
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
1.1
1.2
1.2
1.4
ns
ns
ns
ns
Rising edge clock
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
0.7
0.8
0.8
0.8
ns
ns
ns
ns
Rising edge clock
Rising edge clock
Rising edge clock
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
AT40K05
AT40K10
AT40K20
AT40K40
0.8
0.9
1.0
1.1
ns
ns
ns
ns
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
AT40K05
AT40K10
AT40K20
AT40K40
0.5
0.5
0.5
0.5
ns
ns
ns
ns
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
AT40K05
AT40K10
AT40K20
AT40K40
3.0
3.7
4.3
5.6
ns
ns
ns
ns
From any pad to Global
Set/Reset network
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
8.3
8.4
8.6
8.8
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Fast Clock to Output
tPD (Maximum)
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
7.9
8.0
8.1
8.3
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
27
0896C–FPGA–04/02
ATMEL [ ATMEL ]
