AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Core
Parameter
Path
-2
Units
Notes
2-input Gate
3-input Gate
3-input Gate
4-input Gate
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
DFF
t
PD (Maximum)
x/y -> x/y
x/y/z -> x/y
x/y/w -> x/y
x/y/w/z -> x/y
y -> y
1.8
2.1
2.2
2.2
1.4
1.7
1.8
1.5
2.2
2.3
2.3
1.7
1.8
2.2
2.2
1.8
1.5
1.4
1.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
t
PD (Maximum)
PD (Maximum)
tPD (Maximum)
t
t
PD (Maximum)
PD (Maximum)
x -> y
y -> x
tPD (Maximum)
x -> x
t
t
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
w -> y
w -> x
z -> y
z -> x
q -> x/y
R -> x/y
S -> x/y
q -> w
DFF
tPD (Maximum)
DFF
t
t
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
PZX (Maximum)
PXZ (Maximum)
DFF
Incremental -> L
Local Output Enable
Local Output Enable
x/y -> L
oe -> L
oe -> L
1 unit load
1 unit load
25
0896C–FPGA–04/02
ATMEL [ ATMEL ]
