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90USB82-16MU 参数 Datasheet PDF下载

90USB82-16MU图片预览
型号: 90USB82-16MU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8 / 16K字节 [8-bit Microcontroller with 8/16K Bytes of ISP Flash]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 306 页 / 2299 K
品牌: ATMEL [ ATMEL ]
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18.6.3  
USART MSPIM Control and Status Register n B - UCSRnB  
Bit  
7
6
5
4
3
2
-
1
-
0
-
RXCIEn  
R/W  
0
TXCIEn  
R/W  
0
UDRIE  
R/W  
0
RXENn  
R/W  
0
TXENn  
R/W  
0
UCSRnB  
Read/Write  
Initial Value  
R
1
R
1
R
0
• Bit 7 - RXCIEn: RX Complete Interrupt Enable  
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt  
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is  
written to one and the RXCn bit in UCSRnA is set.  
• Bit 6 - TXCIEn: TX Complete Interrupt Enable  
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt  
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is  
written to one and the TXCn bit in UCSRnA is set.  
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable  
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will  
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written  
to one and the UDREn bit in UCSRnA is set.  
• Bit 4 - RXENn: Receiver Enable  
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override  
normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the  
receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)  
has no meaning since it is the transmitter that controls the transfer clock and since only master  
mode is supported.  
• Bit 3 - TXENn: Transmitter Enable  
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port  
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to  
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,  
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-  
mitted. When disabled, the Transmitter will no longer override the TxDn port.  
• Bit 2:0 - Reserved Bits in MSPI mode  
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,  
these bits must be written to zero when UCSRnB is written.  
180  
AT90USB82/162  
7707D–AVR–07/08  
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