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90USB82-16MU 参数 Datasheet PDF下载

90USB82-16MU图片预览
型号: 90USB82-16MU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8 / 16K字节 [8-bit Microcontroller with 8/16K Bytes of ISP Flash]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 306 页 / 2299 K
品牌: ATMEL [ ATMEL ]
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AT90USB82/162  
Assembly Code Example(1)  
USART_Init:  
clr r18  
out UBRRnH,r18  
out UBRRnL,r18  
; Setting the XCKn port pin as output, enables master mode.  
sbi XCKn_DDR, XCKn  
; Set MSPI mode of operation and SPI data mode 0.  
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)  
out UCSRnC,r18  
; Enable receiver and transmitter.  
ldi r18, (1<<RXENn)|(1<<TXENn)  
out UCSRnB,r18  
; Set baud rate.  
; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!  
out UBRRnH, r17  
out UBRRnL, r18  
ret  
C Code Example(1)  
void USART_Init( unsigned int baud )  
{
UBRRn = 0;  
/* Setting the XCKn port pin as output, enables master mode. */  
XCKn_DDR |= (1<<XCKn);  
/* Set MSPI mode of operation and SPI data mode 0. */  
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);  
/* Enable receiver and transmitter. */  
UCSRnB = (1<<RXENn)|(1<<TXENn);  
/* Set baud rate. */  
/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled  
*/  
UBRRn = baud;  
}
Note:  
1. See “About Code Examples” on page 7.  
18.5 Data Transfer  
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in  
the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation  
of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling  
the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.  
When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given  
the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer  
clock.  
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-  
ing to the UDRn I/O location. This is the case for both sending and receiving data since the  
177  
7707D–AVR–07/08  
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