AT90USB64/128
PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.
• SS/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals
shown in Figure 10-5 on page 78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source..
Table 10-7. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/PCINT7/OC0A/
OC1C
PB6/PCINT6/OC
1B
PB5/PCINT5/OC PB4/PCINT4/OC
1A
2A
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC0/OC1C ENABLE
OC1B ENABLE
OC1A ENABLE
OC2A ENABLE
OC0/OC1C
OC1B
OC1A
OC2A
PCINT7 • PCIE0
PCINT6 • PCIE0
PCINT5 • PCIE0
PCINT4 • PCIE0
1
1
1
1
PCINT7 INPUT
–
PCINT6 INPUT
–
PCINT5 INPUT
–
PCINT4 INPUT
–
AIO
Table 10-8. Overriding Signals for Alternate Functions in PB3..PB0
PB3/PD0/PCINT3/
MISO
PB2/PDI/PCINT2/
MOSI
PB1/PCINT1/
SCK
PB0/PCINT0/
SS
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPE • MSTR
PORTB1 • PUD PORTB0 • PUD
SPE • MSTR
0
SPE • MSTR
0
0
0
SPE • MSTR
SPE • MSTR
SPE • MSTR
SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT
PCINT1 •
PCINT0 •
PCIE0
DIEOE
DIEOV
DI
PCINT3 • PCIE0
1
PCINT2 • PCIE0
1
PCIE0
1
1
SPI MSTR INPUT
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
SCK INPUT
SPI SS
PCINT1 INPUT
PCINT0 INPUT
AIO
–
–
–
–
83
7593A–AVR–02/06
ATMEL [ ATMEL ]
