AT90USB64/128
Table 10-11. Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name
PC3/A11/T.3
PC2/A10
PC1/A9
PC0/A8
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
0
0
0
0
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
1
1
1
1
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
A11
A10
0
A9
0
A8
0
0
0
0
0
0
T3 input
–
–
–
–
AIO
–
–
–
10.3.5
Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 10-12.
Table 10-12. Port D Pins Alternate Functions
Port Pin
PD7
Alternate Function
T0 (Timer/Counter0 Clock Input)
T1 (Timer/Counter1 Clock Input)
XCK1 (USART1 External Clock Input/Output)
ICP1 (Timer/Counter1 Input Capture Trigger)
PD6
PD5
PD4
PD3
INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)
INT2/RXD1 (External Interrupt2 Input or USART1 Receive Pin)
PD2
INT1/SDA/OC2B (External Interrupt1 Input or TWI Serial DAta or Output
Compare for Timer/Counter2)
PD1
PD0
INT0/SCL/OC0B (External Interrupt0 Input or TWI Serial CLock or Output
Compare for Timer/Counter0)
The alternate pin configuration is as follows:
• T0 – Port D, Bit 7
T0, Timer/Counter0 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock
is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1
operates in Synchronous mode.
85
7593A–AVR–02/06
ATMEL [ ATMEL ]
