AT90USB64/128
Figure 27-4. General Port Pin Schematic Diagram
See Boundary-scan
Description for Details!
PUExn
PUD
Q
D
DDxn
Q CLR
WDx
RDx
RESET
OCxn
Q
D
Pxn
PORTxn
ODxn
Q CLR
WRx
RRx
IDxn
RESET
SLEEP
SYNCHRONIZER
RPx
D
Q
D
L
Q
Q
PINxn
Q
CLK I/O
PUD:
PULLUP DISABLE
WDx:
RDx:
WRITE DDRx
PUExn:
OCxn:
ODxn:
IDxn:
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
READ DDRx
WRx:
RRx:
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
RPx:
SLEEP:
CLK I/O :
27.6.2
Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 27-5 is
inserted for the 5V reset signal.
Figure 27-5. Observe-only Cell
To
Next
ShiftDR
Cell
From System Pin
To System Logic
FF1
0
1
D
Q
From
ClockDR
Previous
Cell
347
7593A–AVR–02/06
ATMEL [ ATMEL ]
