AT90USB64/128
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
Bit
7
DAT D7
R/W
0
6
DAT D6
R/W
0
5
DAT D5
R/W
0
4
DAT D4
R/W
0
3
DAT D3
R/W
0
2
DAT D2
R/W
0
1
DAT D1
R/W
0
0
DAT D0
R/W
0
UEDATX
Read/Write
Initial Value
• 7-0 - DAT7:0 -Data Bits
Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
BYCT D10 BYCT D9 BYCT D8 UEBCHX
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - BYCT10:8 - Byte count (high) Bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is
provided by the UEBCLX register.
Bit
7
6
5
4
3
2
1
0
BYCT D7 BYCT D6 BYCT D5 BYCT D4 BYCT D3 BYCT D2 BYCT D1 BYCT D0 UEBCLX
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• 7-0 - BYCT7:0 - Byte Count (low) Bits
Set by the hardware. BYCT10:0 is:
- (for IN endpoint) increased after each writing into the endpoint and decremented after each
byte sent,
- (for OUT endpoint) increased after each byte sent by the host, and decremented after each
byte read by the software.
Bit
7
-
6
5
4
3
2
1
0
EPINT D6 EPINT D5 EPINT D4 EPINT D3 EPINT D2 EPINT D1 EPINT D0 UEINT
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPINT6:0 - Endpoint Interrupts Bits
Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding
endpoint interrupt enable bit is set.
291
7593A–AVR–02/06
ATMEL [ ATMEL ]
