• after “N” write into UEDATX
• as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
22.15.1.1
Abort
An “abort” stage can be produced by the host in some situations:
• In a control transaction: ZLP data OUT received during a IN stage,
• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
• ...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 22-1. Abort flow
Endpoint
Abort
Clear
Disable the TXINI interrupt.
UEIENX.
TXINE
Abort is based on the fact
No
NBUSYBK
=0
that no banks are busy,
meaning that nothing has to
be sent.
Yes
Kill the last written
bank.
Endpoint
reset
KILLBK=1
Wait for the end of the
procedure.
Yes
KILLBK=1
No
Abort done
22.16 Isochronous mode
For Isochronous IN endpoints, it is possible to automatically switch the banks on each start of
frame (SOF). This is done by setting ISOSW. The CPU has to fill the bank of the endpoint; the
bank switching will be automatic as soon as a SOF is seen by the hardware.
A clear of FIFOCON does not have any effects in this mode.
In the case that a SOF is missing (noise on USB pad, ...), the controller will automatically build
internally a “pseudo” start of frame and the bank switching is made. The SOFI interrupt is trig-
gered and the frame number FNUM10:0 is increased.
22.16.1 Underflow
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
278
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
