AT90USB64/128
21. USB controller
21.1 Features
• Support full-speed and low-speed.
• Support ping-pong mode (dual bank)
• 832 bytes of DPRAM.
• 1 endpoint 64 bytes max (default control endpoint),
• 1 endpoints of 256 bytes max, (one or two banks),
• 5 endpoints of 64 bytes max, (one or two banks)
21.2 Block Diagram
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of an internal
PLL. The PLL generates the internal high frequency (48 MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1, to satisfy the USB frequency accuracy and jitter, only these sources clock allow
proper functionnality of the USB controller).
The 48MHz clock is used to generate a 12 MHz Full-speed (or 1 MHz Low-Speed bit clock from
the received USB differential data and to transmit data according to full or low speed USB device
tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is com-
pliant with the jitter specification of the USB bus.
To comply the USB DC characteristics, USB Pads (D+ or D-) should be powered within the 3.0
to 3.6V range. As AT90USB64/128 can be powered up to 5.5V, an internal regulator can insure
the USB pads power supply.
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7593A–AVR–02/06
ATMEL [ ATMEL ]
