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90USB1287-16AU 参数 Datasheet PDF下载

90USB1287-16AU图片预览
型号: 90USB1287-16AU
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机具有ISP功能的Flash和USB控制器64 / 128K字节 [Microcontroller with 64/128K Bytes of ISP Flash and USB Controller]
分类和应用: 微控制器
文件页数/大小: 434 页 / 3172 K
品牌: ATMEL [ ATMEL ]
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AT90USB64/128  
20.9 Multi-master Systems and Arbitration  
If multiple masters are connected to the same bus, transmissions may be initiated simulta-  
neously by one or more of them. The TWI standard ensures that such situations are handled in  
such a way that one of the masters will be allowed to proceed with the transfer, and that no data  
will be lost in the process. An example of an arbitration situation is depicted below, where two  
masters are trying to transmit data to a Slave Receiver.  
Figure 20-21. An Arbitration Example  
VCC  
Device 1  
MASTER  
TRANSMITTER  
Device 3  
SLAVE  
RECEIVER  
Device 2  
MASTER  
TRANSMITTER  
Device n  
R1  
R2  
........  
SDA  
SCL  
Several different scenarios may arise during arbitration, as described below:  
• Two or more masters are performing identical communication with the same Slave. In this  
case, neither the Slave nor any of the masters will know about the bus contention.  
• Two or more masters are accessing the same Slave with different data or direction bit. In this  
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters  
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.  
Losing masters will switch to not addressed Slave mode or wait until the bus is free and  
transmit a new START condition, depending on application software action.  
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the  
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose  
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are  
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,  
depending on the value of the READ/WRITE bit. If they are not being addressed, they will  
switch to not addressed Slave mode or wait until the bus is free and transmit a new START  
condition, depending on application software action.  
This is summarized in Figure 20-22. Possible status values are given in circles.  
245  
7593A–AVR–02/06  
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