14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
Bit
7
6
5
4
3
2
1
0
–
–
ICIE3
–
OCIE3
C
OCIE3B
OCIE3A
TOIE3
TIMSK3
Read/Write
Initial Value
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 69.) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 69.) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 69.) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 69.) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page 69.) is executed when the TOVn Flag, located in TIFRn, is set.
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
Bit
7
6
5
4
–
R
0
3
2
1
0
–
–
ICF1
OCF1C
R/W
0
OCF1B
R/W
0
OCF1A
R/W
0
TOV1
R/W
0
TIFR1
Read/Write
Initial Value
R
0
R
0
R/W
0
14.10.20 Timer/Counter3 Interrupt Flag Register – TIFR3
Bit
7
–
R
0
6
–
R
0
5
4
–
R
0
3
2
1
0
ICF3
R/W
0
OCF3C
R/W
0
OCF3B
R/W
0
OCF3A
R/W
0
TOV3
R/W
0
TIFR3
Read/Write
Initial Value
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
148
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
