AT90USB64/128
14.10.13 Output Compare Register 3 B – OCR3BH and OCR3BL
Bit
7
6
5
4
3
2
1
0
OCR3B[15:8]
OCR3B[7:0]
OCR3BH
OCR3BL
Read/Write
Initial Value
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
14.10.14 Output Compare Register 3 C – OCR3CH and OCR3CL
Bit
7
6
5
4
3
2
1
0
OCR3C[15:8]
OCR3C[7:0]
OCR3CH
OCR3CL
Read/Write
Initial Value
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 120.
14.10.15 Input Capture Register 1 – ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1[7:0]
R/W
ICR1H
ICR1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
14.10.16 Input Capture Register 3 – ICR3H and ICR3L
Bit
7
6
5
4
3
2
1
0
ICR3[15:8]
ICR3[7:0]
R/W
ICR3H
ICR3L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 120.
14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1
Bit
7
6
5
4
3
2
1
0
–
–
ICIE1
–
OCIE1
C
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
Initial Value
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
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