AT90USB64/128
Table 14-4. Waveform Generation Mode Bit Description(1)
WGMn2
(CTCn)
WGMn1
WGMn0
Timer/Counter Mode of
Update of
OCRnx at
TOVn Flag
Set on
Mode
WGMn3
(PWMn1) (PWMn0) Operation
TOP
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
Immediate
TOP
MAX
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
Immediate
TOP
Fast PWM, 8-bit
TOP
Fast PWM, 9-bit
TOP
TOP
Fast PWM, 10-bit
TOP
TOP
PWM, Phase and Frequency
Correct
8
9
1
1
0
0
0
0
0
1
ICRn
BOTTOM
BOTTOM
BOTTOM
BOTTOM
PWM, Phase and Frequency
Correct
OCRnA
10
11
12
13
14
15
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PWM, Phase Correct
PWM, Phase Correct
CTC
ICRn
OCRnA
ICRn
–
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
MAX
(Reserved)
–
Fast PWM
ICRn
OCRnA
TOP
TOP
TOP
Fast PWM
TOP
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
14.10.3 Timer/Counter1 Control Register B – TCCR1B
Bit
7
6
5
–
R
0
4
3
2
1
0
ICNC1
R/W
0
ICES1
R/W
0
WGM13
R/W
0
WGM12
R/W
0
CS12
R/W
0
CS11
R/W
0
CS10
R/W
0
TCCR1B
Read/Write
Initial Value
14.10.4 Timer/Counter3 Control Register B – TCCR3B
Bit
7
6
5
–
R
0
4
3
2
1
0
ICNC3
R/W
0
ICES3
R/W
0
WGM33
R/W
0
WGM32
R/W
0
CS32
R/W
0
CS31
R/W
0
CS30
R/W
0
TCCR3B
Read/Write
Initial Value
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
143
7593A–AVR–02/06
ATMEL [ ATMEL ]
