AT90S1200
External Interrupts
The External Interrupt is triggered by the INT0 pin. The interrupt can trigger on rising
edge, falling edge or low level. This is set up as described in the specification for the
MCU Control Register (MCUCR). When INT0 is level triggered, the interrupt is pending
as long as INT0 is held low.
The interrupt is triggered even if INT0 is configured as an output. This provides a way to
generate a software interrupt.
The interrupt flag can not be directly accessed by the user. If an external edge-triggered
interrupt is suspected to be pending, the flag can be cleared as follows.
1. Disable the External Interrupt by clearing the INT0 flag in GIMSK.
2. Select level triggered interrupt.
3. Select desired interrupt edge.
4. Re-enable the external interrupt by setting INT0 in GIMSK.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (9 bits) is pushed onto the Stack. The vector is normally a
relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt
occurs during execution of a multi-cycle instruction, this instruction is completed before
the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (9 bits) is popped back from the Stack and the I-flag
in SREG is set. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if
more than three nested subroutines and interrupts are executed, only the most recent
three return addresses are stored.
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0838H–AVR–03/02
ATMEL [ ATMEL ]
