Functional Description
Figure 26 shows a detailed structure of the SPI Module.
Figure 26. SPI Module Block Diagram
Internal Bus
SPDAT
Shift Register
FCLK PERIPH
7
6
5
4
3
2
1
0
/4
/8
/16
/32
/64
Clock
Divider
Receive Data Register
Pin
Control
Logic
MOSI
MISO
/128
Clock
Logic
M
S
SCK
SS
Clock
Select
SPR2
SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
8-bit bus
SPI
Control
1-bit signal
SPI Interrupt Request
SPSTA
-
-
-
-
-
SPIF WCOL
MODF
Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI Module is made
through one register:
•
The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
•
•
•
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 27).
70
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
