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89C51RB2-UM 参数 Datasheet PDF下载

89C51RB2-UM图片预览
型号: 89C51RB2-UM
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K字节的闪存 [8-bit Microcontroller with 16K/ 32K Bytes Flash]
分类和应用: 闪存微控制器
文件页数/大小: 127 页 / 1478 K
品牌: ATMEL [ ATMEL ]
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AT89C51RB2/RC2  
drive the network. The Master may select each Slave device by software through port  
pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be  
selected at a time by the Master for a transmission.  
In a Master configuration, the SS line can be used in conjunction with the MODF flag in  
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and  
SCK (see Error conditions).  
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.  
The SS pin could be used as a general-purpose if the following conditions are met:  
The device is configured as a Master and the SSDIS control bit in SPCON is set.  
This kind of configuration can be found when only one Master is driving the network  
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in  
the SPSTA will never be set(1).  
The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This  
kind of configuration can happen when the system comprises one Master and one  
Slave only. Therefore, the device should always be selected and there is no reason  
that the Master uses the SS pin to select the communicating Slave device.  
Note:  
1. Clearing SSDIS control bit does not clear MODF.  
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because  
in this mode, the SS is used to start the transmission.  
Baud Rate  
In Master mode, the baud rate can be selected from a baud rate generator which is con-  
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is  
selected from one of seven clock rates resulting from the division of the internal clock by  
2, 4, 8, 16, 32, 64 or 128.  
Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0.  
Table 54. SPI Master Baud Rate Selection  
SPR2  
SPR1  
SPR0  
Clock Rate  
CLK PERIPH /2  
CLK PERIPH /4  
CLK PERIPH/8  
Baud Rate Divisor (BD)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F
2
4
F
F
8
FCLK PERIPH /16  
FCLK PERIPH /32  
FCLK PERIPH /64  
16  
32  
64  
F
CLK PERIPH /128  
Don’t Use  
128  
No BRG  
69  
4180E–8051–10/06  
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