AT89C51RB2/RC2
Table 53. KBLS Register
KBLS - Keyboard Level Selector Register (9Ch)
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit
Bit
Number
Mnemonic Description
Keyboard Line 7 Level Selection Bit
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
Keyboard Line 6 Level Selection Bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
Keyboard Line 5 Level Selection Bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
Keyboard Line 4 Level Selection Bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
Keyboard Line 3 Level Selection Bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
Keyboard Line 2 Level Selection Bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
Keyboard Line 1 Level Selection Bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
Keyboard Line 0 Level Selection Bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
67
4180E–8051–10/06
ATMEL [ ATMEL ]
