Figure 31. SPI Interrupt Requests Generation
SPIF
SPI Transmitter
CPU Interrupt Request
SPI
CPU Interrupt Request
MODF
SPI Receiver/error
CPU Interrupt Request
SSDIS
Registers
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON)
•
•
•
•
•
•
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
Table 56 describes this register and explains the use of each bit
Table 56. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit Mnemonic
Description
Serial Peripheral Rate 2
7
SPR2
SPEN
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
6
5
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
SSDIS
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated.
Serial Peripheral Master
4
3
MSTR
CPOL
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
2
CPHA
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
74
AT89C51RB2/RC2
4180E–8051–10/06
ATMEL [ ATMEL ]
