Registers
Table 32. SCON Register
SCON (S:98h)
Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic Description
Framing Error bit (SMOD0 = 1)
7
6
FE
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Serial port Mode bit 0 (SMOD0 = 0)
Refer to SM1 for serial port mode selection.
SM0
Serial port Mode bit 1
SM0 SM1 Mode
Baud Rate
0
0
1
1
0
1
0
1
Shift Register FXTAL/12 (or FXTAL/6 in mode X2)
SM1
8-bit UART
9bit UART
9bit UART
Variable
XTAL/64 or FXTAL/32
Variable
F
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
5
4
3
2
SM2
REN
TB8
RB8
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver bit 8/Ninth bit Received in Modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
Transmit Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
1
0
TI
Receive Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and
Figure 23. in the other modes.
RI
Reset Value = 0000 0000b
bit addressable
52
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
