Figure 22. UART Timing in Mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start
bit
Data Byte
Stop
bit
RI
SMOD0 = x
FE
SMOD0 = 1
Figure 23. UART Timing in Modes 2 and 3
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start
bit
Data Byte
Ninth Stop
bit bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces-
sor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, the user can enable the automatic address recognition feature in mode 1.
In this configuration, the stop bit takes the place of the ninth data bit. bit RI is set only
when the received command frame address matches the device’s address and is termi-
nated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in the SADDR register; the
SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form
the device’s given address. The don’t-care bits provide the flexibility to address one or
more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
50
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
