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89C5115-TISUM 参数 Datasheet PDF下载

89C5115-TISUM图片预览
型号: 89C5115-TISUM
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PDSO28, SOIC-28]
分类和应用: 时钟ATM异步传输模式微控制器光电二极管外围集成电路
文件页数/大小: 113 页 / 730 K
品牌: ATMEL [ ATMEL ]
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Overview of FM0  
Operations  
The CPU interfaces the Flash memory through the FCON register and AUXR1 register.  
These registers are used to:  
Map the memory spaces in the adressable space  
Launch the programming of the memory spaces  
Get the status of the Flash memory (busy/not busy)  
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column  
latches space is made accessible by setting the FPS bit in FCON register. Writing is  
possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a  
page while bits 14 to 7 are used to select the programming address of the page.  
Setting FPS bit takes precedence on the EEE bit in EECON register.  
The other memory spaces (user, extra row, hardware security) are made accessible in  
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-  
dance with Table 21. A MOVC instruction is then used for reading these spaces.  
Table 21. FM0 blocks Select bits  
FMOD1  
FMOD0  
FM0 Adressable Space  
User (0000h-3FFFh)  
Extra Row(FF80h-FFFFh)  
Hardware Security Byte (0000h)  
Reserved  
0
0
1
1
0
1
0
1
Launching Programming  
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific  
sequence must be written in these bits to unlock the write protection and to launch the  
programming. This sequence is 5xh followed by Axh. Table 22 summarizes the memory  
spaces to program according to FMOD1:0 bits.  
Table 22. Programming Spaces  
Write to FCON  
FPL3:0  
FPS  
FMOD1  
FMOD0  
Operation  
5
x
0
0
No action  
User  
Write the column latches in user  
space  
A
5
x
x
x
0
0
0
0
1
1
No action  
Extra Row  
Write the column latches in extra row  
space  
A
Hardware  
Security  
Byte  
5
x
x
1
1
0
0
No action  
A
Write the fuse bits space  
5
x
x
1
1
1
1
No action  
No action  
Reserved  
A
Note:  
The sequence 5xh and Axh must be executing without instructions between them other-  
wise the programming is aborted.  
Interrupts that may occur during programming time must be disabled to avoid any spuri-  
ous exit of the programming mode.  
34  
AT89C5115  
4128F–8051–05/06  
 
 
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