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89C5115-TISUM 参数 Datasheet PDF下载

89C5115-TISUM图片预览
型号: 89C5115-TISUM
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PDSO28, SOIC-28]
分类和应用: 时钟ATM异步传输模式微控制器光电二极管外围集成电路
文件页数/大小: 113 页 / 730 K
品牌: ATMEL [ ATMEL ]
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AT89C5115  
Status of the Flash Memory  
The bit FBUSY in FCON register is used to indicate the status of programming.  
FBUSY is set when programming is in progress.  
Selecting FM1  
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.  
Loading the Column Latches  
Any number of data from 1 byte to 128 Bytes can be loaded in the column latches. This  
provides the capability to program the whole memory by byte, by page or by any number  
of Bytes in a page.  
When programming is launched, an automatic erase of the locations loaded in the col-  
umn latches is first performed, then programming is effectively done. Thus no page or  
block erase is needed and only the loaded data are programmed in the corresponding  
page.  
The following procedure is used to load the column latches and is summarized in  
Figure 14:  
Save then disable interrupt and map the column latch space by setting FPS bit.  
Load the DPTR with the address to load.  
Load Accumulator register with the data to load.  
Execute the MOVX @DPTR, A instruction.  
If needed loop the three last instructions until the page is completely loaded.  
unmap the column latch and Restore Interrupt  
35  
4128F–8051–05/06  
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