Table 18. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
7
-
6
-
5
4
-
3
2
0
1
-
0
ENBOOT
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
ENBOOT(1) Set this bit to map the boot Flash between F800h -FFFFh
Clear this bit to disable boot Flash.
Reserved
4
3
-
The value read from this bit is indeterminate. Do not set this bit.
GF3
0
General Purpose Flag 3
Always Zero
2
1
0
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
-
Reserved for Data Pointer Extension
Data Pointer Select bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
DPS
Reset Value = XXXX 00X0b
Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming
section.
28
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
