13.3 Watchdog Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and E1h into
the WDTRST register. As soon as it is enabled, there is no way except the chip reset to disable
it. If it is not cleared using the previous sequence, the WDT overflows and forces a chip reset.
This overflow generates a high level 96 oscillator periods pulse on the RST pin to globally reset
the application. (refer to Section “Power Management”, page 48)
The WDT time-out period can be adjusted using WTO2:0 Bits located in the WDTPRG register
accordingly to the formula shown in Figure 13-3. In this formula, WTOval represents the decimal
value of WTO2:0 Bits. Table 48 reports the time-out period depending on the WDT frequency.
Figure 13-3. WDT Time-Out Formula
6
⋅ (214
⋅ )
2WTOval
WDTTO
=
FWDT
Table 46. WDT Time-Out Computation
FWDT (ms)
WTO2 WTO1 WTO0
6 MHz(1)
16.38
8 MHz(1)
12.28
24.57
49.14
98.28
196.56
393.1
786.24
1572
10 MHz(1)
9.83
12 MHz(2)
8.19
16 MHz(2)
6.14
20 MHz(2)
4.92
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.77
19.66
16.38
12.28
9.83
65.54
39.32
32.77
24.57
19.66
131.07
262.14
524.29
1049
78.64
65.54
49.14
39.32
157.29
314.57
629.15
1258
131.07
262.14
524.29
1049
98.28
78.64
196.56
393.12
786.24
157.29
314.57
629.15
2097
Notes: 1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
FWDT = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode when WTX2 = 0: FWDT = FOSC
.
13.3.1
WDT Behavior During Idle and Power-down Modes
Operation of the WDT during power reduction modes deserves special attention.
The WDT continues to count while the AT89C5132 are in Idle mode. This means that the user
must dedicate some internal or external hardware to service the WDT during Idle mode. One
approach is to use a peripheral Timer to generate an interrupt request when the Timer over-
flows. The interrupt service routine then clears the WDT, reloads the peripheral Timer for the
next service period and puts the AT89C5132 back into Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting and to
hold its count. The WDT resumes counting from where it left off if the Power-down mode is ter-
minated by INT0, INT1 or keyboard interrupt. To ensure that the WDT does not overflow shortly
after exiting the Power-down mode, it is recommended to clear the WDT just before entering
Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
58
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
