AT89C5132
13. Watchdog Timer
The AT89C5132 implement a hardware Watchdog Timer (WDT) that automatically resets the
chip if it is allowed to time out. The WDT provides a means of recovering from routines that do
not complete successfully due to software or hardware malfunctions.
13.1 Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in
Figure 13-1, the 14-bit prescaler is fed by the WDT clock detailed in section "Watchdog Clock
Controller", page 57.
The Watchdog Timer Reset register (WDTRST, see Table 47) provides control access to the
WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 48) provides time-out
period programming.
Three operations control the WDT:
•
•
•
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific two-byte sequence to the WDTRST register clears and enables the WDT.
Figure 13-1. WDT Block Diagram
14-bit Prescaler
7-bit Counter
WDT
CLOCK
To internal
reset
÷ 6
OV
RST
RST
SET
WTO2:0
WDTPRG.2:0
1Eh-E1h Decoder
EN
System
Reset
RST
MATCH
OSC
CLOCK
Pulse Generator
RST
WDTRST
13.2 Watchdog Clock Controller
As shown in Figure 13-2 the WDT clock (FWDT) is derived from either the peripheral clock (FPER
)
or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register. These clocks are
issued from the Clock Controller block as detailed in section "Clock Controller", page 12. When
WTX2 bit is set, the WDT clock frequency is fixed and equal to the oscillator clock frequency
divided by 2. When cleared, the WDT clock frequency is equal to the oscillator clock frequency
divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.
Figure 13-2. WDT Clock Controller and Symbol
PER
CLOCK
0
WDT
CLOCK
WDT Clock
1
OSC
CLOCK
÷
2
WDT Clock Symbol
WTX2
CKCON.6
57
4173E–USB–09/07
ATMEL [ ATMEL ]
