AT89C5132
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
INPUT
OUTPUT
Min
Max
Min
Max
Symbol
HD; STA
Parameter
(4)
(4)
(4)
T
Start condition hold time
SCL low time
14·TCLCL
16·TCLCL
14·TCLCL
1 µs
4.0 µs(1)
4.7 µs(1)
4.0 µs(1)
T
LOW
THIGH
SCL high time
(2)
TRC
SCL rise time
-
T
FC
SCL fall time
0.3 µs
0.3 µs(3)
20·TCLCL(4)- TRD
1 µs(1)
T
SU; DAT1
SU; DAT2
SU; DAT3
HD; DAT
SU; STA
SU; STO
Data set-up time
250 ns
250 ns
250 ns
0 ns
T
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
(4)
T
8·TCLCL
T
8·TCLCL(4) - TFC
4.7 µs(1)
(4)
T
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
1 µs
4.0 µs(1)
(4)
(4)
T
T
BUF
4.7 µs(1)
(2)
TRD
SDA rise time
-
T
FD
SDA fall time
0.3 µs
0.3 µs(3)
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maxi-
mum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
23.3.4.2
Waveforms
Figure 23-16. Two Wire Waveforms
Repeated START condition
START or Repeated START condition
START condition
Tsu;STA
STOP condition
Trd
0.7 VDD
SDA
(INPUT/OUTPUT)
0.3 VDD
Tsu;STO
Tsu;DAT3
Tbuf
Tfd
Trc
Tfc
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thigh
Tsu;DAT2
Tlow
Thd;STA
Thd;DAT
Tsu;DAT1
167
4173E–USB–09/07
ATMEL [ ATMEL ]
