18.6.3
Reset Address
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast
addresses are XXXX XXXXb(all don’t-care bits). This ensures that the Serial Port is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
18.7 Interrupt
The Serial I/O Port handles two interrupt sources that are the “end of reception” (RI in SCON)
and “end of transmission” (TI in SCON) flags. As shown in Figure 18-16 these flags are com-
bined together to appear as a single interrupt source for the C51 core. Flags must be cleared by
software when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are glo-
bally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and whether the framing error detection is enabled or not, RI
flag is set during the stop bit or during the ninth bit as detailed in Figure 18-17.
Figure 18-16. Serial I/O Interrupt System
SCON.0
RI
Serial I/O
Interrupt Request
TI
SCON.1
ES
IEN0.4
Figure 18-17. Interrupt Waveforms
a. Mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
8-bit Data
Stop Bit
RI
SMOD0 = X
FE
SMOD0 = 1
b. Mode 2 and 3
D2 D3
RXD
D0
D1
D4
D5
D6
D7
D8
Start bit
9-bit data
Stop bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
18.8 Registers
Table 91. SCON Register
116
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
