Table 28. MMC Clock Selection
MMCCKS2:0
000
Clock Selection (FS)
FOSC (default)
60 MHz
001
010
48 MHz
011
30 MHz
100
24 MHz
101
20 MHz
110
16 MHz
111
FOSC ÷ 2
Table 29. MMC Clock Divider
MMCDIV4:0
00000
Clock Division
Disabled (no clock out)
≥ 00001
FMMC = FS ÷ MMCDIV
SIO Clock Generator
As detailed in Figure 23, the SIO clock which feeds the internal SIO baud rate generator
can be programmed using SIOCKS bit in CKSEL register according to Table 30 to gen-
erate either the oscillator frequency or a very high frequency allowing very high baud
rate when PLL is enabled. SIO clock is enabled by SIOCKEN bit in CKEN register.
Figure 23. SIO Clock Generator Block Diagram and Symbol
CKEN.1
SIOCKEN
OSC
0
1
FS
SIO Clock
CLOCK
GEN
120 MHz
SIO
CLOCK
SIOCKS
CKSEL.2
SIO Clock Symbol
Table 30. SIO Clock Selection
SIOCKS
Clock Selection (FS)
FOSC
0
1
120 MHz
32
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
