Special Function Registers
SFR Pagination
The AT85C51SND3Bx implement a SFR pagination mechanism which allows mapping
of high number of peripherals in the SFR space. As shown in Figure 24, four pages are
accessible through the PPCON (Peripheral Pagination Control) register (see Table 37).
The four bits of PPCON: PPS0 to PPS3 are used to select one page as detailed in Table
36. Setting one bit of PPCON using the setb instruction automatically clears the 7 oth-
ers: e.g. if page 0 is selected, selecting page 3 is done by the instruction setb PPS3
which clears PPS0.
By default, after reset selected page is page 0.
The PPCON content is automatically saved in a specific stack at each interrupt service
routine entry during vectorization and restored at exit during reti execution.
Figure 24. SFR Pagination Block diagram
PPS0
PPCON.0
0
2
1
2
PPS1
PPCON.1
3
PPS2
PPCON.2
PPS3
PPCON.3
Table 36. Page Selection Truth Table
PPS3
PPS2
PPS1
PPS0
Selected Page
0
X
X
X
1
0
X
X
1
0
X
1
0
0
0
1
0
0
0
Page 0
Page 0
Page 1
Page 2
Page 3
0
Table 37. PPCON Register
PPCON (Y.C0h) – Peripheral Page Control Register
7
6
5
4
3
2
1
PPS1
0
-
-
-
-
PPS3
PPS2
PPS0
Bit
Bit
Number
Mnemonic Description
Reserved
7-4
3-0
-
The value read from these bits is always 0. Do not set these bits.
Peripheral Page Select Bits
PPS3:0
Refer to Table 36 for page decoding information.
Reset Value = 0000 0001b
36
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
