AT85C51SND3Bx
Figure 18. PLL Block Diagram and Symbol
Up
N Divider
PFLD
480 MHz
CHP
VCO
Down
PLLN3:0
PLLCLK.3:0
12 MHz
16 MHz
20 MHz
00
01
10
11
Primary
Divider
FREV
R Divider
PLL
CLOCK
PLLCKS1:0
CKSEL.4:3
PLLR3:0
PLLCLK.7:4
PLL Clock Symbol
Table 24. PLL Reverse Clock Selection
PLLCKS1:0
Clock Selection (FREV)
00
01
10
11
12 MHz (default)
16 MHz
20 MHz
12 MHz ÷ (PLLR + 1)
PLL Programming
The PLL is programmed depending on the oscillator clock frequency. In order to mini-
mize the output jitter, FREV must be as higher as possible. Table 26 shows the PLL
programming values and reverse frequency depending on some oscillator frequency.
Table 25. PLL Programming Values versus Input Frequency
FOSC (MHz)
PLLCKS1:0
PLLN3:0 / N
0000
PLLR3:0 / R
XXXX
FREV (MHz)
12
13
00
11
01
11
11
10
00
11
12
1
1100 / 13
0000
1011 / 12
XXXX
16
16
2.4
1.5
20
12
2
19.2
19.5
20
0111 / 8
1100 / 13
0000
0100 / 5
0111 / 8
XXXX
24
0001 / 2
1100 / 13
XXXX
26
0101 / 6
System Clock Generator In order to increase the system computation throughput, it is possible to switch the sys-
tem clock to higher value when PLL is enabled. System clock generator block diagram
is shown in Figure 19 and is based on a frequency selector controlled by SYSCKS1:0
bits in CKSEL (see Table 34) according to Table 26.
The CPU clock can be disabled by entering the idle reduction mode as detailed in the
Section “Power Management”, page 18.
Note:
In order to prevent any incorrect operation while dynamically switching the system fre-
quency, user must be aware that all peripherals using the peripheral clock as time
reference (timers, etc…) will have their time reference modified by this frequency
change.
29
7632A–MP3–03/06
ATMEL [ ATMEL ]
