Figure 19. System Clock Generator Block Diagram and Symbols
Audio Controller
Clock
OSC
CLOCK
00
24 MHz
30 MHz
40 MHz
FSYS
01
10
11
0
1
÷ 2
Peripheral
Clock
CLOCK
GEN
CPU Core
Clock
SYSCKS1:0
CKSEL.1:0
X2
CKCON.0
IDL
PCON.0
AUD
CLOCK
PER
CLOCK
CPU
CLOCK
Audio Clock Symbol
Peripheral Clock Symbol
CPU Core Clock Symbol
Table 26. System Clock Selection
SYSCKS1:0
Clock Selection (FSYS)
00
01
10
11
FOSC (default)
24 MHz
30 MHz
40 MHz
X2 Feature
Unlike standard C51 products that require 12 clock periods per machine cycle, the
AT85C51SND3Bx need only 6 clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit(1) in CKCON and allows the
AT85C51SND3Bx to operate in 6 or 12 clock periods per machine cycle. As shown in
Figure 19, both CPU and peripheral clocks are affected by this feature. Figure 20 shows
the X2 mode switching waveforms. After reset the standard mode is activated. In stan-
dard mode the CPU and peripheral clock frequency is the oscillator frequency divided by
2 while in X2 mode, it is the oscillator frequency.
Figure 20. Mode Switching Waveforms
FSYS
FSYS ÷ 2
X2 bit
Clock
STD Mode
X2 Mode
STD Mode
DFC/NFC Clock
Generator
In order to optimize the data transfer throughput between the DFC and the NFC, both
peripherals share the same clock frequency. The DFC and NFC clock generator block
diagram is shown in Figure 21 and is based on a frequency selector.
Frequency selection is done using DNFCKS2:0 bits in CKSEL (see Table 33) according
to Table 27.
Frequency is enabled by setting DNFCKEN bit in CKEN.
30
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
