Bit
Bit
Number
Mnemonic Description
End Of Reset Interrupt Flag
Set by hardware when an “End Of Reset” has been detected by the USB
controller. This triggers an USB interrupt if EORSTE is set.
3
EORSTI
Shall be cleared by software. Setting by software has no effect.
Start Of Frame Interrupt Flag
2
1
SOFI
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected
(every 1 ms). This triggers an USB interrupt if SOFE is set.
Micro-Start Of Frame Interrupt Flag
MSOFI
Set by hardware when an USB “Micro-Start Of Frame” PID (µSOF) has been
detected (every 125 µs). This triggers an USB interrupt if MSOFE is set.
Suspend Interrupt Flag
Set by hardware when an USB “Suspend” ‘idle bus for 3 frame periods: a J state
for 3 ms) is detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section “Suspend, Wake-Up and Resume” for more details.
0
SUSPI
Reset Value = 0000 0000b
Table 114. UDIEN Register
UDIEN (1.DAh) – USB Device Global Interrupt Enable Register
7
6
5
4
3
2
1
0
-
UPRSME
EORSME WAKEUPE
EORSTE
SOFE
MSOFE
SUSPE
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from these bits is always 0. Do not set these bits.
Upstream Resume Interrupt Enable Bit
UPRSME
EORSME
WAKEUPE
EORSTE
SOFE
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
End Of Resume Interrupt Enable Bit
5
4
3
2
1
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
Wake-Up CPU Interrupt Enable Bit
Set to enable the WAKEUPI interrupt.
Clear to disable the WAKEUPI interrupt.
End Of Reset Interrupt Enable Bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
Start Of Frame Interrupt Enable Bit
Set to enable the SOFI interrupt.
Clear to disable the SOFI interrupt.
Micro-Start Of Frame Interrupt Enable Bit
MSOFE
Set to enable the MSOFI interrupt.
Clear to disable the MSOFI interrupt.
116
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
