Figure 133. Format and States in the Master Transmitter Mode
MT
Successful transmis-
sion to a slave receiver
S
SLA
W
A
Data
A
P
08h
18h
28h
Next transfer started with
a repeated start condition
S
SLA
W
R
10h
Not acknowledge received
after the slave address
A
P
MR
20h
Not acknowledge received
after a data Byte
A
P
30h
Arbitration lost in slave
address or data Byte
Other master
continues
Other master
continues
A or A
A or A
38h
A
38h
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
68h 78h B0h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
nnh
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
186
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
