Registers
Table 160. SCON Register
SCON (S:98h) – Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
OVR/SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic Description
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
FE
7
Serial Port Mode Bit 0
Refer to Table 158 for mode selection.
SM0
SM1
Serial Port Mode Bit 1
Refer to Table 158 for mode selection.
6
5
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address
recognition features.
SM2
Clear to disable the multiprocessor communication and automatic address
recognition features.
Receiver Enable Bit
4
3
REN
TB8
Set to enable reception.
Clear to disable reception.
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit
received.
2
RB8
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
Transmit Interrupt Flag
1
0
TI
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
RI
Reset Value = 0000 0000b
178
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
