Bulk/Interrupt
Transactions
Bulk and Interrupt transactions are managed in the same way.
Bulk/Interrupt OUT
Transactions in Standard
Mode
Figure 70. Bulk/Interrupt OUT transactions in Standard Mode
UFI
C51
HOST
OUT DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
Endpoint FIFO Read Byte 2
OUT DATA1
OUT DATA1
NAK
NAK
Endpoint FIFO Read Byte n
Clear RXOUTB0
DATA1
OUT
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
An endpoint should be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data Bytes by reading the UBYCTX register. If
the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal
to 0 and no data has to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-
point. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will
answer a NAK handshake for each OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint Byte counter contains the number of Bytes sent by the Host.
110
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
